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2019年11月

2019年11月29日 (金)

The SCL is entered into each individual EEPROM device

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The SCL input is accustomed to beneficial edge clock knowledge into each individual EEPROM gadget and adverse edge clock info away from every device.

SERIAL Information (SDA): The SDA pin is bidirectional for serial facts transfer. This pin is open-drain driven and should be wire-ORed with any quantity of other open-drain or open- collector gadgets.

DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device deal with inputs which can be challenging wired for your AT24C01A and the AT24C02. As several as eight 1K/2K products might be tackled on a one bus program (device addressing is reviewed in detail under the Unit Addressing part).

The AT24C04 employs the A2 and A1 inputs for tough wire addressing along with a total of 4 4K products could be dealt with over a one bus system. The A0 pin is really a no join and might be linked to ground.

The AT24C08A only employs the A2 enter for hardwire addressing and also a whole of two 8K gadgets could be addressed with a single bus program. The A0 and A1 pins are not any connects and will be connected to floor.

The AT24C16A doesn't utilize the gadget tackle pins, which boundaries the quantity of devices on the solitary bus to 1. The A0, A1 and A2 pins aren't any connects and may be linked to floor.

2019年11月22日 (金)

To be sure the productive usage of your microchip merchandise

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The Devices Details and Update Line providessystem end users a listing with the most recent versions of all ofMicrochip's progress devices application solutions.

Additionally, this line offers info on how customerscan receive quite possibly the most current enhance kits.

092002DS21189F-page 1924AA64/24LC64READER RESPONSEIt is our intention to deliver you together with the greatest documentation probable to make sure prosperous use of your Microchip prod-uct.

If you want to offer your opinions on group, clarity, issue issue, and ways that our documentationcan greater serve you.

Be sure to listing the following facts, and use this define to deliver us along with your reviews about this document.

1. Do you know the best attributes of the doc?

two. How can this doc meet your hardware and computer software improvement requires?

three. Does one discover the firm of this doc easy to adhere to? Otherwise, why?

4. What additions for the document does one feel would improve the structure and topic?

five. What deletions with the doc could possibly be designed with no impacting the general usefulness?

six. Is there any incorrect or misleading information and facts (what and wherever)

seven. How would you make improvements to this document?

2019年11月12日 (火)

2002 Microchip Technology Inc

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 24AA64/24LC642.0 FUNCTIONAL DESCRIPTIONThe 24XX64 supports a bi-directional 2-wire bus anddata transmission protocol. A device that sends dataonto the bus is defined as transmitter, and a devicereceiving data as receiver.

  The bus has to be controlledby a master device which generates the serial clock(SCL), controls the bus access and generates theSTART and STOP conditions, while the 24XX64 worksas slave. Both master and slave can operate as trans-mitter or receiver, but the master device determineswhich mode is activated.3.0 BUS CHARACTERISTICSThe following bus protocol has been defined:

  Data transfer may be initiated only when the bus is not busy.

  During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition.Accordingly, the following bus conditions have beendefined (Figure 3-1).3.1 Bus not Busy (A)Both data and clock lines remain HIGH.3.2 Start Data Transfer (B)A HIGH to LOW transition of the SDA line while theclock (SCL) is HIGH determines a START condition.

  Allcommands must be preceded by a START condition.3.3 Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while theclock (SCL) is HIGH determines a STOP condition. Alloperations must be ended with a STOP condition.3.4 Data Valid (D)The state of the data line represents valid data when,after a START condition, the data line is stable for theduration of the HIGH period of the clock signal.The data on the line must be changed during the LOWperiod of the clock signal.

  There is one clock pulse perbit of data.Each data transfer is initiated with a START conditionand terminated with a STOP condition. The number ofthe data bytes transferred between the START andSTOP conditions is determined by the master deviceand is theoretically unlimited, although only the last six-teen will be stored when doing a write operation. Whenan overwrite does occur it will replace data in a first-infirst-out (FIFO) fashion.

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